Very interesting, thank you. So we're basically not nearly as close to "true" 7nm as I thought? Do companies like TSMC already have a plan as to how to deal with "true" 7nm or is a lot more research still needed?
According to this video using an electron scanning microscope on amd and Intel chips, the “7nm” or “10nm” number does not measure anything, and is effectively a process version number for marketing. From memory there is no single number for measuring transistors or efficiency, transistor density is useful, but it doesn’t tell you the performance or power usage.
Moore's law always was an economic roadmap. Everything in the semiconductor industry is (was) planned around the transistor density doubling every two years, from hardware investments, to market segmentation, to microarchitecture design, to software optimizations. So I think it makes sense that they go on with pushing transistor density from generation to generation, and convey it to the public using names it is already familiar with.
It's right that power has severely limited performance despite increasing the transistor density lately. Maybe we'll once again get better with adiabatic computing?
Both performance and power usage are physically functions of transistor density. Assuming the apples-to-apples comparison of similar transistor counts, operating TDPs, and processor designs.
>Do companies like TSMC already have a plan as to how to deal with "true" 7nm or is a lot more research still needed?
If you will forgive the expression. Yes and No.
Yes in that TSMC has ideas / plans scaling all the way to 0.8nm, targeting 2030. That is only a few steps above what you described as true 7nm.
No in that no one knows if it will work. We know Quantum Tunnelling will hit some day, some where, some how, at some percentage.
Remember you are talking about leading edge Semi-Conductor manufacturing. Nothing like this has ever been done before.
It is a bit like telling me 5G today was possible when I was researching on first gen 3G two decades ago. If you describe to me with theory I will have properly said yes..... but it is hard to imagine how it will actually be implemented.
Technically it’s figured out. Gate-all-around has been experimentally demonstrated at pitches less than FinFET. The primary problem is, who is going to pay it. The economics are very tough at these 1s of nm nodes but hopefully that’s only a transitory problem.
You are talking about GAA at 2nm, I was talking about sub 1nm ( Node naming ) Tech. Which the OP was referring to "true" 7nm or Gate pitch / metal pitch at sub 7nm. We are still quite far away from figuring those out.
But yes, I agree the economics model is tough as I have been stating on various forums for years. That is part of the reason why we see Semi-conductors consolidation, like Marvell, Broadcom.
My best guess is that some time in 2026/ 28 we might have to stretch the cycle to three years instead of two. Giving more time to amortised those cost. But HyperScaler Cloud Market seems to be not limited by any R&D funding so I am actually quite optimistic we could see the current 2 year cadence all the way to 2030. Anything beyond is just too hard to predict or infer.
To make transistors smaller, and not just draw them with finer resolution, the industry will need a new way of controlling the channel. FinFET got us here. Most likely gate-all-around will be the technique that gets the “true” geometries smaller.
