> 250 MHz in 1993 is insanity, considering that was the 33 MHz 486 era.
I think the 250 MHz ones appeared later on, in subsequent revisions. Still, one of the promises of RISC was that, since the logic was much simpler, you could jack up clock rates further than it was possible with CISC designs.
Much the same promise is made by VLIW today - it should let you "jack up" core counts and clock rates compared to even RISC, because you don't need to do energy-intensive OOO reordering and speculation so it becomes feasible to avoid thermal and power constraints even with otherwise heavy CPU use. (The clearest issue with it is that it leaks way too much of your μarch choices in the programming model, so every ISA is inherently bespoke.)
I think the 250 MHz ones appeared later on, in subsequent revisions. Still, one of the promises of RISC was that, since the logic was much simpler, you could jack up clock rates further than it was possible with CISC designs.